The invention relates generally to a circuit for monitoring the bit error integrity of a digital data system and converting it to the bit error rate.
In electronic data transmissions, the quality or reliability of the transmission system may be expressed in terms of a bit error rate, i.e., the number of erroneously received digital pulses per unit of time divided by the data rate of the communication channel. The bit error rate is determined by a number of factors including intersystem interference, noise, fading, equipment misadjustment and the like.
One prior art method of improving the quality of a data transmission channel has been through the use of automatic gain control in the receivers. Provisions are made to switch channels when the gain control feedback signal exceeds certain limits. While this method can detect a weak or faded signal, signal distortion due to noise is not identified and may go undetected.
Another method employs the transmission of a known pattern of data as a means for checking the received data for accuracy. Of course, this drawback to the technique is that normal transmissions on the channel being checked must be interrupted for transmission of the known pattern.
It is often necessary, particularly in the case of "hot standby" and diversity systems to have a continuous rapid response and reasonably accurate estimate of whether the bit error rate of a digital system such as a digital radio exceeds some predetermined threshold. This estimate should include the effects of degradation in alignment of the modulator, RF and IF circuit, the carrier recovery, phase detector and clock recovery portion of the demodulators and the effects of distortion. Such an estimate in prior art could be obtained in the "mod demod section" by using a pseudo-error detector. The pseudo-error detector provides a measure of the quality of the eye pattern and from this measurement a close approximation of the actual bit error rate could be extrapolated. Reference may be made to U.S. Pat. No. 3,721,959 and also to copending application, "Automatic Clock Positioning Circuit For A Digital Data Transmission System", Ser. No. 965,960, filed on Dec. 4, 1978, and assigned to the assignee of the present invention which discusses further the use of pseudo-error detectors as an on-line means of monitoring the bit error integrity.
For further discussion relating to error detection, reference may be made to: D. J. Godding, "Performance Monitor Techniques for Digital Receivers Based on Extrapolation of Error Rate", IEEE Transactions on Communication Technology, Vol. COM-16, pp. 380-387, June 1968; S. B. Weinstein, "Estimation of Small Probabilities by Linearization of the Tail of a Probability Distribution Function", IEEE Transactions on Communication Technology, Vol. COM-19, pp. 1149-1155, December 1971; and, B. J. Leon, H. L. Hammond, Jr., P. A. Vena, W. E. Sears, III and R. T. Kitahara, "A Bit Error Rate Monitor for Digital PSK Links", IEEE Transactions on Communications, Vol. COM-23, pp. 518-525, May 1975, which detail analytical studies of the subject, especially when related to FSK, BPSK and WPSK signals, and broadly to all forms of digital transmission.
Although the above references provide techniques for detecting error rates and pseudo-error rates, they fail to provide a digital means for measuring the bit error rate on-line without switching modes of operation. It has been found that the bit error rate which cannot be measured when in service can be related by the techniques disclosed herein, to the bit error integrity which can, by use of the disclosed circuit, be measured and an alarm can be given indicating the degradation of a communication channel and thus allow an operator to take corrective action such as the switching of communication channels.